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16-bit 500 ksps pulsar ? unipolar adc with reference ad7666 rev. 0 informatio n fur n ish e d b y a n alo g d e vic e s is believe d to be accurate a n d reliab le. how e ver, n o resp on sibili ty is assumed by an alog devices f o r its use, n o r fo r a n y i n fri n geme nt s of p a t e nt s or ot he r ri ght s o f th ird parties th at m a y result fro m its use. specifications subject to chan g e with out n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e un der a n y p a t e nt or p a t e nt ri ght s of anal og dev i c e s. tra d emark s an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 2.5 v internal r e ference: typic a l drift 3 ppm/ c guarantee d m a x drift 15 ppm/c throughput: 500 ksps inl: 2.0 lsb max (0.0 038 % of full scale) 16-bit resolut i on with no missing codes s/(n+d): 88 db min @ 20 khz thd: C9 6 db m a x @ 2 0 k hz analog input voltage range: 0 v to 2.5 v both ac and dc specifications n o pipeline delay parallel and se rial 5 v/3 v inte rface spi ? /qspi tm /mi c rowire tm /dsp compatible single 5 v supp ly operation power dissipati o n 66 mw t y p, 13 2 w @ 1 ks ps without ref 8 1 m w ty p w i th r e f 48-lea d lqfp a n d 48- lead lfc s p packages pin-to-pin compatible with pu lsar a d cs applic ati o ns data acq u isitio n medical instr u ments digital signal processing spectrum anal ysis instrumentation battery-powered systems process control general description the ad7666* is a 16-b i t, 500 ks ps, c h a r g e r e dis t r i b u tion sar a n alog-t o-d i g i ta l co n v er t e r th a t o p era t es f r o m a sin g le 5 v p o we r su p p ly . t h e p a r t c o n t ains a hig h sp e e d, 1 6 -bi t s a m p l i ng ad c, an in t e r n al co n v ersion c l o c k, in t e r n al r e f e r e n c e , er r o r co r r e c t i o n cir c ui ts, an d b o t h s e r i a l and p a r a l l el sy stem i n te r - face p o r t s. th e ad7666 is ha r d wa r e fac t o r y-cal i b r a t e d and c o m p re he ns ivel y te ste d to e n su re ac p a r a me te rs su ch as s i g n a l - to - n oi s e r a t i o ( s n r ) a n d tot a l h a r m on i c d i stor t i on ( t h d ) , i n addi t i o n to t h e m o r e t r ad i t io na l dc p a r a m e ters o f ga in, o f fs et, a nd li n e a r i t y . the ad7666 is a v a i la b l e in a 48 -lead l q fp an d a tin y 48-lead lfcs p , w i t h op era t io n sp e c if ie d f r o m C40c to +85c. * p a te nt p e nd ing. func tio n a l block di agram 03034- 0- 001 switched cap dac 16 control logic an d calibration circuitry clock ad7666 data[15:0] busy rd cs ser/par ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst ref refbufin pdbuf pdref byteswap f i gur e 1 . f u nctio n al bl oc k dia g r a m table 1. pulsa r selection t y p e / k s p s 1 0 0 C 2 5 0 5 0 0 C 5 7 0 800C 1000 pseudo- differential ad7651 ad7660 / ad7661 ad7650 / ad7652 ad7664 / ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel / simultaneous ad7654 ad7655 product highlights 1. fa s t t h r o u g hpu t . the ad7666 is a 500 ks ps, c h arg e r e dis t r i b u tion, 16-b i t sar ad c wi t h in t e r n al er r o r co r r ec tio n cir c ui tr y . 2. sup e r i o r i n l . the ad7666 has a maxim u m in t e g r al n o nlin ea r i ty o f 2.0 ls b wi th n o mis s in g 16-b i t co des. 3. int e r n a l r e f e r e n c e . the ad7666 has a n in t e r n al r e f e r e n c e wi th a ty p i cal t e m p era t ur e dr i f t o f 3 p p m / c. 4. s i ng l e - supp l y o p e r a t i o n . the ad7666 o p era t es f r o m a sin g le 5 v s u p p l y . i t s p o w e r dissi p a t io n d e cr e a s e s wi t h t h r o ug h p u t . 5. se ri al o r p a r a ll e l i n t e rf a c e . v e rs a t ile p a ral l el o r 2-wir e s e r i a l in t e r f ace a r ra n g em e n t is co m p a t i b le wi th bo th 3 v a nd 5 v log i c.
ad7666 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 16 converter operation .................................................................. 16 typical connection diagram ................................................... 18 power dissipation versus throughput .................................... 20 conversion control .................................................................... 21 digital interface .......................................................................... 22 parallel interface ......................................................................... 22 serial interface ............................................................................ 22 master serial interface ............................................................... 23 slave serial interface .................................................................. 24 microprocessor interfacing ....................................................... 26 application hints ........................................................................... 27 bipolar and wider input ranges .............................................. 27 layout .......................................................................................... 27 evaluating the ad7666s performance .................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history revision 0: initial version
ad7666 rev. 0 | page 3 of 28 specifications table 2. C40c to +85c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted parameter conditions min typ max unit resolution 16 bits analog input voltage range v in C v ingnd 0 v ref v operating input voltage v in C0.1 +3 v v ingnd C0.1 +0.5 v analog input cmrr f in = 10 khz 65 db input current 500 ksps throughput 7.7 a input impedance 1 throughput speed complete cycle 2 s throughput rate 0 500 ksps dc accuracy integral linearity error C2.0 +2.0 lsb 2 no missing codes 16 bits differential linearity error C1.0 +1.5 lsb transition noise 0.7 lsb unipolar zero error, t min to t max 3 5 lsb unipolar zero error temperature drift 0.5 ppm/c full-scale error, t min to t max 3 ref = 2.5 v 0.08 % of fsr full-scale error temperature drift 1.4 ppm/c power supply sensitivity avdd = 5 v 5% 2 lsb ac accuracy signal-to-noise f in = 20 khz 88 89.2 db 4 spurious free dynamic range f in = 20 khz 96 107 db total harmonic distortion f in = 20 khz C106 C96 db signal-to-(noise + distortion) f in = 20 khz 88 89.1 db C60 db input, f in = 20 khz 30 db C3 db input bandwidth 12 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 750 ns reference internal reference voltage v ref @ 25c 2.493 2.5 2.507 v internal reference temperature drif t C40c to +85c 3 15 ppm/c output voltage hysteresis C40c to +85c 50 ppm long term drift 100 ppm/1000 hours line regulation avdd = 5 v 5% 15 ppm/v turn-on settling time c ref = 10 f 5 ms temperature pin voltage output @ 25c 300 mv temperature sensitivity 1 mv/c output resistance 4 k? external reference voltage range 2.3 2.5 avdd C 1.85 v external reference current drain 500 ksps throughput 120 a
ad7666 rev. 0 | page 4 of 28 parameter conditions min typ max unit digital inputs logic levels v il C0.3 +0.8 v v ih 2.0 dvdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 7 v operating current 500 ksps throughput avdd 8 with reference and buffer 12.2 ma avdd 9 reference and buffer alone 3 ma dvdd 10 4.1 ma ovdd 10 102 a power dissipation without ref 8 , 10 500 ksps throughput 66 75 mw 1 ksps throughput 132 w power dissipation with ref 8 , 10 500 ksps throughput 81 90 mw temperature range 11 specified performance t min to t max C40 +85 c 1 see an section. alog input 2 lsb means least significant bit. with the 0 v to 2.5 v input range, 1 lsb is 38.15 v. 3 see the de section. these specifications do not include the error contribution from the external ref erence. finitions of specifications 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 5 parallel or serial 16-bit. 6 conversion results are available imme diately after completed conversion. 7 the max should be the minimu m of 5.25 v and dvdd + 0.3 v. 8 with ref, pdref and pdbuf are low; wi thout ref, pdref and pdbuf are high. 9 with pdref, pdbuf low and pd high. 10 tested in parallel reading mode. 11 consult factory for extended temperature range.
ad7666 rev. 0 | page 5 of 28 timing specifications table 3. C40c to +85c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted parameter symbol min typ max unit refer to figure 33 and figure 34 convert pulse width t 1 10 ns time between conversions t 2 2 s cnvst low to busy high delay t 3 35 ns busy high all modes except master serial read after convert t 4 1.25 s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 1.25 s acquisition time t 8 750 ns reset pulse width t 9 10 ns refer to figure 35, figure 36, and figure 37 (parallel interface modes) cnvst low to data valid delay t 10 1.25 s data valid to busy low delay t 11 12 ns bus access request to data valid t 12 45 ns bus relinquish time t 13 5 15 ns refer to figure 39 and figure 40 (master serial interface modes) 1 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay 1 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 525 ns sync asserted to sclk first edge delay t 18 3 ns internal sclk period 2 t 19 25 40 ns internal sclk high 2 t 20 12 ns internal sclk low 2 t 21 7 ns sdout valid setup time 2 t 22 4 ns sdout valid hold time 2 t 23 2 ns sclk last edge to sync delay 2 t 24 3 ns cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 2 t 28 see table 4 cnvst low to sync asserted delay t 29 1.25 s sync deasserted to busy low delay t 30 25 ns refer to figure 41 and figure 42 (slave serial interface modes) 1 external sclk setup time t 31 5 ns external sclk active ed ge to sdout delay t 32 3 18 ns sdin setup time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns 1 in serial interface mode, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 2 in serial master read during co nvert mode. see table 4 for serial master read after convert mode.
ad7666 rev. 0 | page 6 of 28 table 4. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 18 3 17 17 17 ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7 21 49 99 ns sdout valid setup time minimum t 22 4 18 18 18 ns sdout valid hold time minimum t 23 2 4 30 80 ns sclk last edge to sync delay minimum t 24 3 55 130 290 ns busy high width maximum t 24 2 2.5 3.5 5.75 s
ad7666 rev. 0 | page 7 of 28 absolute maximum ratings table 5. ad7666 stress ratings 1 parameter rating in 2 , temp 2 , ref, refbufin, ingnd, refgnd to agnd avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dvdd + 0.3 v pdref, pdbuf 3 20 ma internal power dissipation 4 700 mw internal power dissipation 5 2.5 w junction temperature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating co nditions for extended pe riods may affect device reliability. 2 see analog input section. 3 see the voltage reference input section. 4 specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w 5 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf * * in serial interface modes,the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise,the load is 60pf maximum. 03033-0-002 figure 2. load circuit for digital interface timing, sdout, sync, sclk outputs c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 03033-0-003 figure 3. voltage reference levels for timing esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equi pment and can discharge without detection. although this product fe atures proprietary esd protection ci rcuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7666 rev. 0 | page 8 of 2 8 pin conf iguration and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/2c nc nc nc = no connect ser/ par d0 d1 busy d15 d14 d13 ad7666 d3/divsclk1 d12 d4 /e x t / i nt d 5 /in vsyn c d6/invscl k d7 /rdc/s d i n ognd ovdd dv dd dgnd d8 /s dout d9 /s cl k d 10/syn c d1 1 / rde rror p dbuf p dre f re fbufin temp av dd in agnd agnd nc ingnd re fgnd re f 03034-0-004 d2/divsclk0 f i g u re 4. 48-l e ad l qfp (st - 4 8 ) and 48 -l ead lfcs p (c p - 4 8 ) ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 description 1, 36, 41, 42 agnd p analog power g r ound pin. 2, 44 avdd p input analog power pin. nominally 5 v. 3, 6, 7, 40 n c n o c o n n e c t . 4 b y t e s w a p d i paralle l m o d e selection ( 8 -/16- bit) . when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when h i gh, the lsb is output on d[1 5 :8 ] and the msb is output on d[7:0 ] . 5 ob/ 2c di straight binary/binary twos complement. whe n ob/ 2c is high, t h e digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output fr om its internal sh ift register. 8 ser/ par di serial/pa r al lel s e lection input. when low, the pa rallel port is selected; when h i gh, the serial interface mode is selected and some bits of the data bus are us ed as a serial po rt. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel po rt data output bu s. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3]or divsclk[0:1] di/o when ser/ par is low, these output s are used as bit 2 and bit 3 of th e parallel port data output bus. when ser/ par is high, ext/ int is low, and rdc/sdin is low (s erial m a ster read after convert), these inputs, part of the serial po rt, are used to slo w d o wn, if d e sire d, the internal serial clock that clocks the data output. in other seri al m o des, these pin s are not used. 13 d4 or ext/ int di/o when ser/ par is low, this output is us ed as bit 4 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used as a digital select i n put for choosi n g the internal data clock or an ext e rnal data cl ock. with ex t/ int tied l o w, the internal clock is selected on the sclk output. with ex t/ int set to a logic high, output data i s synchro n ized to an externa l clock signa l con n ected to the s c lk input. 14 d5 or invsync di/o when ser/ par is low, this output is us ed as bit 5 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. it is activ e in both master and slave mode s. when low, sync is active high. when high, sync is active low. 15 d6 or invsclk di/o when ser/ par is low, this output is us ed as bit 6 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used to invert the sc lk signal. it is active in both master a n d slave mod e s.
ad7666 rev. 0 | page 9 of 28 pin no. mnemonic type 1 description 16 d7 or rdc/sdin di/o when ser/ par is low, this output is us ed as bit 7 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/ sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 21 d8 or sdout do when ser/ par is low, this output is us ed as bit 8 of the parallel port data output bus. when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stor ed in an on-chip register. the ad7666 provides the conversion result, msb first, from its internal shif t register. the data format is determined by the logic level of ob/ 2c . in serial mode when ext/ int is low, sdout is valid on both edges of sclk. in serial mode when ext/ int is high, if invsclk is low, sdout is updated on the sclk rising edge and valid on the next falling edge; if invsclk is high , sdout is updated on the sclk falling edge and valid on the next rising edge. 22 d9 or sclk di/o when ser/ par is low, this output is used as bit 9 of the parallel po rt data or sclk output bus. when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logi c state of the invsclk pin. 23 d10 or sync do when ser/ par is low, this output is us ed as bit 10 of the parallel port data output bus. when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sy nc is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invs ync is high, sync is driven low and remains low while the sdout output is valid. 24 d11 or rderror do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. when ser/ par and ext/ int are high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lo st and rderror is pulsed high. 25C28 d[12:15] do bit 12 to bit 15 of the parallel port data output bus. these pins ar e always outputs regardless of the state of ser/ par . 29 busy do busy output. transitions high when a conversion is started and rema ins high until the conversion is complete and the data is latched into the on-chip shift registe r. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, this pin resets the ad7666 and the current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, pow er consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. the mode is most appropriate if low sampling jitter is desired. if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample/hol d is put into the hold state and a conversion is immediately started. 37 ref ai/o reference input voltage. on-chip reference output voltage. 38 refgnd ai reference input analog ground. 39 ingnd ai analog input ground.
ad7666 rev. 0 | page 10 of 28 pin no. mnemonic type 1 description 43 in ai primary analog input with a range of 0 v to 2.5 v. 45 temp ao temperature sensor voltage output. 46 refbufin ai/o reference input voltage. the re ference output and the reference buffer input. 47 pdref di this pin allows the choice of internal or exte rnal voltage references. when low, the on-chip reference is turned on. when high, the internal refe rence is switched off an d an external reference must be used. 48 pdbuf di this pin allows the choice of buffering an internal or external reference with the internal buffer. when low, the buffer is selected. wh en high, the buffer is switched off. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = digi tal output; p = power.
ad7666 rev. 0 | page 11 of 28 definitions of specifications integr al nonli n earity er ror ( i nl) li n e a r i t y e r r o r r e f e r s t o th e devia t i o n o f ea ch in d i v i d u al code f r o m a line dr a w n f r o m nega t i ve f u l l s c a l e t h ro ug h p o si t i ve f u l l s c ale . th e p o in t us ed as n e g a ti ve f u l l s c ale o c c u rs ? ls b bef o r e th e f i r s t co d e tra n si ti o n . p o si ti v e full scale i s d e f i n e d a s a lev e l 1? l s b b e y o n d th e la s t cod e tra n si ti o n . th e de vi a t i o n i s m e as ur ed f r o m th e middle o f eac h co de t o th e t r ue s t ra ig h t lin e . diffe renti a l n o nlinearity er ror (dnl) i n a n i d e a l a d c , c o d e t r ans i t i ons are 1 l s b a p ar t . d i f f e r e n t i a l n o n l ine a r i ty is t h e m a xim u m d e v i a t ion f r o m t h is ide a l va l u e . i t is o f t e n sp e c if ie d in t e r m s o f r e s o l u t i o n fo r w h i c h n o missin g c o d e s are g u ar a n te e d . full-scale e r ror the las t tra n s i tio n (f r o m 01110 t o 01111 in tw os c o m p l e me n t c o d i ng ) s h ou l d o c c u r for an an a l og volt age 1 ? l s b be lo w t h e n o minal f u l l s c ale (2. 49994278 v f o r th e 0 v t o 2.5 v ra n g e). the f u l l -s cale er r o r is t h e de v i a t io n o f t h e ac t u a l le v e l o f th e la s t tra n si ti o n f r o m th e i d eal lev e l . unipolar z e ro error the f i rs t tra n si t i o n sh o u ld o c c u r a t a le ve l ? ls b a b o v e a n alog g r o u n d (19.073 v f o r th e 0 v to 2.5 v ra n g e). u n i p ola r zer o e r r o r i s th e d e v i a t i o n o f t h e a c t u al tra n si ti o n f r o m th a t po in t . spurio us -fre e dyn a mi c r a n g e ( s fdr ) s f d r is t h e dif f er en ce , i n de c i b e ls (db), b e tw e e n t h e r m s a m pli t ude o f t h e in p u t sig n al and t h e p e a k s p u r io us sig n al . effe c t iv e numb er of bits (eno b) eno b is a m e asur em en t o f t h e r e s o l u t i o n wi t h a sine w a ve in p u t. i t is r e l a t e d t o s /( n + d ) and is exp r es s e d in b i ts b y t h e fol l o w ing fo r m u l a: eno b = ( s /[ n + d ] db C 1.76)/6. 02 total h a rmon i c distortion ( t hd) t h d i s t h e ra tio o f th e rm s s u m o f th e f i r s t f i v e h a rm o n i c co m p on e n ts t o t h e r m s val u e o f a f u l l -s cale in pu t sig n al , an d is exp r es s e d i n de ci b e ls. signal-to-noi s e ratio (snr) s n r is t h e r a t i o o f t h e r m s val u e o f t h e ac t u al i n p u t sig n al t o t h e r m s su m of a l l ot he r sp e c t r a l c o m p o n e n t s b e l o w t h e n y qu i s t f r e q uen c y , excl udin g ha r m o n ics a nd dc. th e val u e fo r s n r is exp r es s e d i n de ci b e ls. signa l -to-(noise + distortion) ra tio (s/[n+ d ]) s/(n+d) is t h e ra t i o o f t h e r m s val u e o f t h e ac t u al in p u t sig n al t o th e rm s s u m o f all o t h e r s p ec tral co m p o n en ts be lo w t h e n y q u ist f r e q ue nc y , in cl udi n g har m o n ics b u t excl udin g dc. the val u e fo r s/(n+d) is exp r es s e d in de c i b e ls. apert u re del a y a p er t u r e de l a y i s a m e as ur e o f t h e ac q u isi t ion p e r f o r ma n c e and is m e a s ur e d f r o m t h e fa l l in g e d ge o f t h e cnv s t in p u t t o w h en t h e i n p u t sig n al is h e l d fo r a co n v ersio n . tra n sient res p onse t r a n sien t r e s p on s e is t h e time r e q u ir ed f o r the ad7666 t o achie v e i t s r a t e d acc u rac y a f t e r a f u l l -s ca le st ep f u n c t i on is a p plie d t o i t s in p u t. refer e n c e voltage te mp er a t ur e coeffi cie n t refer e nce v o l t ag e t e m p era t ur e co ef f i cien t is de r i v e d f r o m t h e max i m u m an d mini m u m r e feren c e o u tp u t vol t a g e ( v ref ) me a s u r e d a t t min , t ( 2 5 c ) , a n d t ma x . i t is exp r es s e d in pp m/c usin g t h e fol l o w in g e q ua t i on: 6 10 ) C ( ) 25 ( ) C ) ) / ( = min max ref ref ref ref t t v ( v ( v c ppm tcv c min max w h er e: v ref ( ma x ) = m a xim u m v ref at t min , t ( 2 5 c ) , o r t max v ref ( mi n ) = m i nim u m v ref at t min , t ( 2 5 c ) , o r t max v ref (25 c ) = v re f a t +25c t ma x = +85c t min = C40c ther m al hysteresis ther mal h y s t eresis is def i n e d as t h e a b s o l u t e maxim u m cha n g e o f r e fer e n c e o u t p u t v o l t a g e a f t e r t h e de vice is c y cle d t h r o ug h t e m p era t ur e f r o m ei t h er t_hy s+ = +25c t o t max t o +25c t_hy sC = +25c t o t min to + 2 5 c i t is exp r es s e d i n p p m usin g t h e fol l o w in g e q u a t i o n : 6 10 ) 25 ( ) _ ( ) 25 ( ) ( ? = c v hys t v c v ppm v ref ref ref hys w h er e: v ref (25 c ) = v re f a t 25c v ref (t _ h ys ) = m a xim u m c h ang e o f v ref a t t _ h y s + o r t _ h y s C .
ad7666 rev. 0 | page 12 of 28 typical perf orm ance cha r acte ristics 03034-0-005 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 inl ( l sb) 0 16384 32768 49152 65536 code f i gure 5 . integr a l no nli n ea ri t y vs . c o d e 03034-0-006 0 0.5 1.0 1.5 2.0 positive inl (lsb) 0 10 20 numbe r of units 15 5 f i gur e 6 . t y pi c a l p o si ti v e inl d i str i but i o n ( 9 9 uni t s) 03034-0-007 0 10 20 30 numbe r of units 0 0.25 0.50 0.75 1.00 1.25 1.50 positive dnl (lsb) f i gur e 7 . t y pi c a l p o si ti v e dnl di str i b u ti o n (99 uni t s) 03034-0-008 ? 1.0 ? 0.5 0 0.5 1.0 1.5 0 16384 32768 49152 65536 code dnl (lsb) f i gur e 8 . d i ffe r e ntia l no nl inea ri t y vs . c o de 03034-0-009 0 20 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 negative inl (lsb) number of units 10 15 5 f i gure 9 . t y pi c a l nega ti v e inl di stri b u ti o n (99 uni t s) 03034-0-010 0 40 ? 1.00 ?0.75 ?0.50 ? 0.25 0 negative dnl (lsb) number of units 20 30 10 f i gure 1 0 . t y pi c a l nega ti v e dnl d i stri b u ti o n ( 9 9 uni t s)
ad7666 rev. 0 | page 13 of 28 03034-0-011 0 20000 40000 60000 80000 100000 120000 counts 7ffe 7fff 8000 8001 8002 8003 7ffd 8004 code in hex 7ffc 0 211 623 4 20187 15968 1 112335 111791 0 f i g u re 11. h i s t og r a m of 2 61, 1 2 0 co nvers i ons of a dc input a t the code t r a n si t i on 03034-0-012 ? 180 ? 160 ? 140 ? 120 ? 100 ?80 ?60 ?40 ?20 0 amplitude (db of full sc a l e ) 0 5 0 100 150 200 250 frequency (khz) f s = 500ksps f in = 101.361khz snr = 88.6db thd = ? 98.1db sfdr = 99.2db s/[n+d] = 88.1db f i g u re 12. fft p l ot 03034-0-013 snr s/[n+d] enob 81 82 83 84 85 86 87 88 89 90 91 snr, s/[n+d] (db) 1 1 0 100 1000 frequency (khz) 13.0 13.5 14.0 14.5 15.0 15.5 enob (bits) fi g u r e 1 3 . s n r , s / ( n + d ) , a n d e n o b v s . fr e q u e n c y 03034-0-014 0 11 2789 3300 34 0 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 counts code in hex 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 148481 53814 52691 f i g u re 14. h i s t og r a m of 2 61, 1 2 0 co nvers i ons of a dc input a t the code c e nt er 03034-0-015 sfdr thd second harmonic third harmonic ? 120 ? 115 ? 110 ? 105 ? 100 ?95 ?90 ?85 ?80 ?75 ?70 thd, harmonics (db) 1 1 0 100 1000 frequency (khz) 20 30 40 50 60 70 80 90 100 110 120 sfdr (db) fi g u r e 1 5 . t h d, h a r m o n i c s , a n d s f d r v s . fr e q u e n c y 03034-0-016 88 89 90 91 ?60 ? 5 0 ? 40 ?30 ? 20 ? 1 0 0 input level (db) snr, s/[n+d] referre d to full-scale (db) snr s/[n+d] f i gure 16. snr and s/(n+d) vs . input l e v e l (referred to f u ll s c ale)
ad7666 rev. 0 | page 14 of 28 03034-0-017 13.0 13.5 14.0 14.5 15.0 15.5 enob ( b it s) 87 88 89 90 92 s nr, s / [n+d] (db) ? 5 5 ? 35 ? 1 5 5 25 45 65 85 105 125 snr s/[n+d] enob temperature ( c) 91 f i g u re 17. snr , s / ( n +d), and e n ob v s . t e mpe r at u r e 03034-0-018 ?115 ?110 ?105 ?100 ?55 ? 35 ?15 5 25 45 65 85 105 125 temperature ( c) thd, harmonics (db) thd second harmonic third harmonic f i g u re 18. th d a n d ha r m on ics v s . t e m p er at u r e 03034-0-019 0.001 0.01 0.1 10 100 1000 10000 100000 10 100 1k 10k 100k 1m sampling rate (sps) op e rating curre nts ( a) 1 dvdd ovdd avdd pdref = pdbuf = high f i gure 19. o p er atin g current v s . s a mp l e ra te 03034-0-020 full-scale error zero error ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 ze ro e rror, full-s cale e rror (ls b ) ?55 ? 35 ? 1 5 5 25 45 65 85 105 125 temperature ( c) f i gure 20. zero e r r o r , f u l l -s c a l e e r r o r w i thout r e fe r e nc e v s . t e mpe r atu r e 03034-0-021 2.4994 2.4996 2.4998 2.5000 2.5002 2.5004 2.5006 2.5008 2.5010 2.5012 2.5014 2.5016 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 120 t e m p e r a t u r e ( c ) vr ef ( v ) f i g u re 21. t y pi c a l r e f e renc e v o lt ag e o u t p ut v s . t e mpe r at ur e ( 2 u n it s ) 03034-0-039 0 5 10 15 20 25 numbe r of units 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 reference drift (ppm/c) 7 . 5 8.0 f i gure 22. r e ference v o ltage t e mpe r at ur e coeffi ci ent d i stributi on ( 9 3 units)
ad7666 rev. 0 | page 15 of 28 03035-0-023 0 5 10 15 20 25 30 35 40 45 50 0 5 0 100 150 200 c l (pf) t 12 de lay (ns ) ovdd = 2.7v @ 25 c ovdd = 2.7v @ 85 c ovdd = 5v @ 85 c ovdd = 5v @ 25 c f i g u re 23. t y pic a l d e lay v s . l oad cap a c i t a nce , c l
ad7666 rev. 0 | page 16 of 28 circuit i n formation sw a comp sw b in ref refgnd lsb msb 32,768c ingnd 16,384c 4c 2c c c 65,536c contr ol logic switches contr o l bu s y output code 03033-0-020 cnvst f i gur e 2 4 . adc simpl i f ie d s c hema ti c the ad7666 is a v e r y fas t , lo w p o w e r , sin g le s u p p l y , p r ecis e 16-b i t a n alog-t o - dig i tal con v er ter (ad c ). th e ad7666 is ca p a b l e o f con ver tin g 100,000 s a m p les p e r s e cond (500 ks ps) a nd a l lo ws p o w e r s a v i n g s b e twe e n con v ersio n s . the ad7666 p r o v ides the us er wi t h an o n -c hi p trac k/h o ld , s u cces si v e a p p r o x ima t ion ad c t h a t do es n o t exhi b i t an y p i p e lin e o r l a t e n c y , making i t ideal f o r m u l t i p l e m u l t i p lexed cha n n e l a p plic a t io n s . the ad7666 can b e o p er a t e d f r o m a sin g l e 5 v s u p p l y a nd c a n be in t e r f ace d t o ei ther 5 v o r 3 v dig i tal log i c. i t is h o us e d in ei t h er a 48-le a d lqfp o r a 48-le ad lfcs p t h a t s a ves sp ace an d al lo ws f l e x i b le c o nf igura t io n s as ei ther a s e r i al or p a ral l e l in t e r - face . th e ad76 66 is p i n-t o -p in co m p a t i b le wi th pu lsar ad cs a nd is an u p g r ade o f t h e ad76 61 a nd ad7664 . converter operation the ad7666 is a s u cces si v e -a p p r o xima tion ad c bas e d on a c h a r g e r e dis t r i b u tio n d a c. f i g u r e 24 s h o w s a s i m p lif i e d s c h e - m a t i c of t h e a d c . t h e c a p a c i t i v e d a c c o ns i s t s of an ar r a y of 16 b i na r y w e ig h t e d ca p a c i to rs and a n a d d i t i o n a l ls b c a p a ci to r . t h e co m p a r a t o r s n e ga ti v e in p u t i s co n n e ct e d t o a d u mm y ca p a c i t o r o f t h e s a me val u e as t h e ca p a c i t i v e d a c a r ra y . d u r i n g t h e ac quisi t io n pha s e , t h e com m o n t e r m ina l o f t h e a r ra y t i e d to t h e c o m p ar a t or ' s p o s i t i v e i n put i s c o n n e c te d to a g n d vi a sw a . a l l in dep e n d e n t s w i t ch es a r e co nne c te d t o t h e a n alog in p u t in. th us, th e ca p a c i t o r a r ra y is us ed as a s a m p ling ca pa ci t o r a n d acq u i r es th e a n alog si gn al o n in . s i m i la r l y , t h e d u mm y c a p a ci to r acq u ir es t h e a n alog sig n al o n in g n d . wh e n cnv s t go es lo w , a con v ersio n phas e is in i t ia t e d . w h en t h e con v ersio n phas e b e g i n s , sw a a nd s w b are op e n e d . t h e ca p a ci t o r a r ra y a n d d u mm y ca p a ci t o r a r e t h en d i sco n n e cted f r o m t h e i n p u t s a nd co nn e c t e d to refgnd . ther efo r e , t h e dif f er en t i al v o l t a g e b e t w e e n in a nd in g n d c a p t ur e d a t t h e e nd o f t h e acq u isi t ion phas e is a p pli e d t o t h e com p ara t o r in p u ts, ca usin g t h e com p a r a t o r t o b e com e u n b a lan c e d . b y swi t c h ing ea c h e l em en t o f th e ca pa ci t o r a r ra y bet w een r e fg n d a n d r e f , t h e com p a r a t o r in p u t va r i es b y b i na r y w e ig h t e d v o l t a g e st eps (v ref /2, v ref /4, v ref /65536). the co n t r o l log i c t o g g l es th es e s w i t c h e s , s t a r t i n g w i th th e m s b , t o b r i n g th e c o m p a r a t o r b a c k in to a b a lan c e d co ndi t i on. af t e r this p r o c es s is co m p lete d , th e con t r o l log i c g e n e r a t e s t h e ad c o u t p ut co de an d b r in gs t h e b u s y o u t p u t lo w .
ad7666 rev. 0 | page 17 of 28 tra n sfer f u nctions ta ble 7. out p ut codes a n d i d ea l input volt a g es digital output code (hex) description analo g input straight binary twos complement fsr C1 lsb 2.499962 v ffff 1 7fff 1 fsr C 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale C 1 lsb 1.249962 v 7fff ffff Cfsr + 1 lsb 38 v 0001 8001 Cfsr 0 v 0000 2 8000 2 us i n g t h e o b / 2c dig i tal in p u t, the ad7666 o f f e rs tw o o u t p u t co din g s: st r a ig h t b i n a r y a n d two s co m p lem e n t . the ls b si ze is v ref /65536, whic h is a b ou t 38.1 5 v . th e ad76 66 s ideal t r a n sfer cha r ac t e r i st ic is sh o w n in f i gur e 25 and t a b l e 7. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (s tra i ght bina ry ) analog input v ref ? 1.5 lsb v ref ? 1 lsb 1l s b 0v 0.5 lsb 1 lsb = v re f / 65536 03033-0-021 1 th i s i s a l so t h e co d e f o r overrange anal og input ( v in C v in g n d above v re f C v re f g nd ). 2 th i s i s a l so t h e co d e f o r underrange analog input (v in below v in g n d ). f i g u re 25. a d c ide a l t r ans f er f u nc t i o n no tes 1 the configuration shown is using the internal reference and internal buffer. 2 the ad8021 is recommended. see driver amplifier choice section. 3 optional low jitter. 4 a 10 f ceramic capacitor (x5r, 1206 size) is recommended (e.g., panasonic ecj3yb0j106m). see voltage reference input section. ad7666 d 3 clock c/ p/ d s p serial por t digit al suppl y (3.3v or 5v) dv d d 100nf + 10 f 100nf + 10 f 20 ? 100nf + 10 f analog suppl y (5v) c c a nalog inpu t (0 v t o 2 . 5 v) pd reset ser/par ob/2c bu s y sdout sclk ingnd in refgnd ref agnd avdd dgnd d v dd o v dd ognd 03034-0-022 u1 2 pdref pdbuf rd cs c n vst refbufin 1 100nf byteswap c r 4 2.7nf 15 ?
ad7666 rev. 0 | page 18 of 28 typical connection diagram f i gur e 26 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7666. analog input f i g u re 2 7 show s an e q u i v a l e n t c i rc u i t of t h e i n put st r u c t u r e of th e ad7666. the tw o dio d es, d1 a nd d2, p r o v ide e s d p r o t e c t i o n fo r t h e a n alog in p u ts in an d i n g n d . c a r e m u s t be ta k e n t o en s u r e tha t t h e a n alog in p u t sig n al ne ver exce e d s th e su p p l y ra ils b y m o r e t h an 0.3 v . this w i l l ca us e t h es e dio d es t o b e come fo r w a r d-b i as e d a nd st a r t co nd u c t i n g c u r r en t. t h es e dio d es can ha ndle a f o r w a r d-b i as e d c u r r en t o f 100 ma maxim u m. f o r in s t an c e , t h es e c o n d i t io ns co u l d e v en t u al l y o c c u r w h e n t h e in p u t b u f f er s (u1) s u p p lies a r e dif f er en t f r o m a v d d . i n s u ch a cas e , an i n p u t b u f f er wi t h a sh or t-cir c ui t c u r r e n t limi t a t i on can b e u s ed t o p r o t ect t h e pa rt . c2 r1 d1 d2 c1 in or ingnd agnd av d d 03033-0-023 f i g u re 27. equiv a le nt a n al og input c i rcuit this a n alog in pu t s t r u c t ur e al lo ws t h e s a m p l i n g o f t h e dif f er en- tial sig n al betw e e n in and ing n d . u n li k e o t her co n v er t e rs, in gnd is s a m p led a t t h e s a m e time as i n . b y usin g this d i f f er en ti al i n p u t , sm all si gn als co m m o n t o bo th i n p u ts a r e re j e c t e d , a s s h ow n i n fi g u re 2 8 , w h i c h re pre s e n t s t h e t y pi c a l cmrr o v er f r e q uen c y wi t h o n -chi p and ext e r n al r e fer e n c es. f o r in s t an ce , b y usin g in gnd to s e n s e a r e m o te sig n al g r o u nd , g r o u n d p o t e n t ia l dif f er en ces b e t w e e n t h e s e n s o r a nd t h e lo cal ad c g r o u nd a r e e l im ina t e d . 03034-0-028 30 40 50 60 70 80 90 1 1 0 100 1000 10000 frequency (khz) cmrr (db) ext ref ref fi g u r e 2 8 . a n a l o g i n p u t c m r r v s . fr e q u e n c y d u r i n g t h e ac quisi t io n phas e , t h e im p e dan c e of t h e a n alog in p u t in c a n be m o de led as a p a ral l e l co m b ina t io n o f ca p a c i t o r c1 a nd t h e n e t w o r k fo r m e d b y t h e s e r i es co nne c t i o n o f r1 and c2. c1 is p r ima r il y th e p i n ca p a ci tan c e . r1 is ty p i cal l y 168 ? a nd is a l u m p e d co m p on e n t ma de u p o f s o me s e r i a l r e sisto r s a nd t h e o n r e sist a n ce o f t h e s w i t ch es. c2 is typ i cal l y 60 pf a n d is ma inl y t h e a d c s a m p lin g ca p a ci t o r . d u r i n g t h e con v ersio n phas e , w h er e t h e sw i t ch es a r e op ene d , t h e i n p u t im p e dan c e is limi te d t o c1. r 1 a nd c2 ma k e a 1-p o le lo w-p a s s f i l t er tha t r e d u ces undesira b l e aliasin g ef fe c t an d limi ts the n o is e . w h en t h e s o ur c e im p e dan c e o f t h e dr ivi n g cir c ui t is lo w , t h e ad7666 can be dr i v en dir e c t l y . l a rg e s o ur ce im p e dan c es wil l si gn i f i c a n tl y a f f e ct th e a c pe rf o r m a n c e , e s peci ally t o tal h a r m on i c d i stor t i on ( t h d ) . t h e m a x i m u m s o u r c e i m p e d a nc e d e pen d s o n th e a m o u n t o f thd th a t ca n b e t o lera t e d . th e thd deg r ades as a f u n c t i on o f t h e s o ur ce im p e d a n c e a nd t h e max i m u m in p u t f r e q uen c y , as sh o w n i n f i gur e 29. 03034-0-029 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 thd (db) 1 1 0 100 1000 input frequency (khz) r s = 20 ? r s = 500 ? r s = 50 ? r s = 100 ? f i g u re 29. th d v s . a n al og input f r equ e nc y and s o urc e r e s i s t anc e driver amplifi e r choice al th o u g h the ad7666 is easy to dr i v e , th e dr i v er a m p l if ier n e e d s t o m e et t h e fol l o w in g r e quir em e n ts: ? the dr i v er am p l if ier a nd the ad7666 a n alog in p u t cir c ui t m u s t be a b le t o s e t t le f o r a f u l l -s cale s t ep o f t h e ca p a c i t o r a r ra y a t a 16-b i t lev e l (0.0015%) . i n the a m p l if ier s da ta s h e e t, s e t t lin g a t 0.1% t o 0.01% is m o r e co mmonl y s p eci- f i e d . this co u l d dif f er sig n if ica n t l y f r o m t h e s e t t lin g t i m e a t a 1 6 - bi t l e vel and s h ou l d b e ve r i f i e d pr i o r to dr ive r se l e cti o n . t h e tin y o p a m p ad8 021 , w h i c h c o m b i n e s u l t r a lo w n o is e and h i g h ga i n -b a ndw id t h , m e e t s t h is s e t t ling ti m e r e q u i r em en t ev e n w h e n used w i t h ga i n s u p t o 13.
ad7666 rev. 0 | page 19 of 28 ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7666. the noise coming from the driver is filtered by the ad7666 analog input circuit, 1-pole, low-pass filter made by r1 and c2 or by the external filter, if one is used. the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3 ) ( 2 784 28 log 20 n db loss ne f snr where: f C3db is the input bandwidth of the ad7666 (13 mhz) or the cutoff frequency of the input filter (3.9 mhz), if one is used. n is the noise factor of the amplifier (+1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. for instance, a driver with an equivalent input noise of 2 nv/hz, like the ad8021 with a noise gain of +1 when configured as a buffer, degrades the snr by only 0.13 db when using the filter shown in figure 26, and by 0.43 db without the filter shown in figure 26. ? the driver needs to have a thd performance suitable to that of the ad7666. figure 15 gives the thd versus frequency that the driver should exceed. the ad8021 meets these requirements and is appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor that should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. the ad8022 could also be used if a dual version is needed and gain of 1 is present. the ad829 is an alternative in applications where high frequency (above 100 khz) performance is not required. in gain of 1 applications, it requires an 82 pf compensation capacitor. the ad8610 is an option when low bias current is needed in low frequency applications. voltage reference input the ad7666 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 v reference. unlike many adcs with internal references, the internal reference of the ad7666 provides excellent performance and can be used in almost all applications. to use the internal reference along with the internal buffer, pdref and pdbuf should both be low. this will produce 1.2 v on refbufin which, amplified by the buffer, will result in a 2.5 v reference on the ref pin. the output impedance of refbufin is 11 k ? (minimum) when the internal reference is enabled. it is necessary to decouple refbufin with a ceramic capacitor greater than 10 nf. thus the capacitor provides an rc filter for noise reduction. to use an external reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows the 2.5 v reference to be applied to refbufin. to use an external reference directly on ref pin, pdref and pdbuf should both be high. pdref and pdbuf power down the internal reference and the internal reference buffer, respectively. note that the pdref and pdbuf input current should never exceed 20 ma. this could eventually occur when input voltage is above avdd (for instance at power up). in this case, a 100 ? series resistor is recommended. the internal reference is temperature compensated to 2.5 v 7 mv. the reference is trimmed to provide a typical drift of 3 ppm/c . this typical drift characteristic is shown in figure 22. for improved drift performance, an external reference, such as the ad780 , can be used. the ad7666 voltage reference input ref has a dynamic input impedance; it should therefore be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr tantalum capacitor connected to ref and refgnd, with minimum parasitic inductance. a 10 f (x5r, 1206 size) ceramic chip capacitor (or 47 f tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: ? the low noise, low temperature drift adr421 and ad780 ? the low power adr291 ? the low cost ad1582
ad7666 rev. 0 | page 20 of 28 f o r a p p l ica t ion s tha t us e m u l t i p le ad7666s, i t is m o r e ef fec t i v e t o us e t h e i n t e r n al b u f f er t o b u f f er t h e r e fer e n c e v o l t a g e . c a r e sh o u ld b e t a k e n wi t h t h e vol t a g e r e fer e n c e s t e m p era t ur e co ef f i cien t, whic h dir e c t l y a f f e c t s th e f u l l -s cale acc u rac y if this pa ra m e ter m a t t er s. f o r in s t a n ce, a 15 p p m /c t e m p era t ur e co ef f i cien t o f t h e r e fer e n c e chan g e s f u l l s c ale b y 1 ls b/c. no t e t h a t v ref c a n be in cr eas e d t o a v d d C 1.85 v . s i n c e the in p u t ra n g e is def i n e d i n t e r m s o f v ref , t h is w o u l d ess e n t ia l l y in cr eas e t h e ra ng e t o 0 v t o 3 v wi t h an a v dd a b o v e 4.85 v . the ad780 c a n b e s e l e c t e d w i t h a 3 v re f e re nc e vo lt age. the temp p i n, which me asur es t h e t e m p era t ur e o f t h e ad7666, can b e us ed as sh o w n in f i gur e 30. the o u t p u t o f temp p i n is a pplie d t o on e o f t h e i n p u ts o f t h e a n alog swi t ch (e .g., ad g779 ), a n d t h e ad c i t s e lf is used t o m e as ur e i t s o w n t e m p era t ur e . this co nf igura t io n is v e r y us ef u l f o r im p r o v in g t h e calib r a t ion acc u rac y o v er t h e t e m p er a t ur e ra n g e . adg779 ad8021 c c 03034-0-024 analog input (unipolar) ad7666 in temperature sensor temp f i gur e 3 0 . t e m p er atur e se nsor co nne c ti o n d i a g r a m power supply the ad7666 us es thr e e p o w e r s u p p l y p i n s : a n analog 5 v s u p p l y a v d d , a d i g i t a l 5 v c o r e s u p p l y d v d d , a n d a d i g i t a l i n p u t / o u t p u t in t e r f ace s u p p l y o v d d . o v d d al lo ws dir e c t in t e r f ace wi t h an y log i c b e tw een 2.7 v and d v d d + 0.3 v . t o r e d u c e the s u p p lies n eeded, th e dig i tal co r e (d vd d) c a n b e s u p p lie d thr o ugh a sim p l e r c f i l t er f r o m th e a n alog s u p p l y , as s h o w n in f i gur e 26. th e ad7666 is in dep e nden t o f p o w e r s u p p l y s e q u e n cin g on c e o v dd do es no t exce e d d v dd b y m o r e t h an 0.3 v , a n d is th us f r ee o f s u p p l y v o l t a g e in d u ce d la t c h-u p . a d di tio n al l y , i t is v e r y in sen s i t i v e t o p o w e r s u p p l y va r i a t io n s o v er a wide f r e q uen c y ra n g e , as s h own in f i gur e 31, whic h r e p r es en ts psr r o v er f r e q uen c y wi t h o n -chi p a n d ext e r n al re f e re nc e s . 03034-0-031 int ref ext ref 30 40 50 60 80 90 1 1 0 100 1000 10000 frequency (khz) psr r ( d b ) 70 fi g u r e 3 1 . p s r r v s . fr e q u e n c y power diss ipatio n ve rsus throughput o p era t ing c u r r en ts a r e v e r y lo w d u r i n g t h e acquisi t io n phas e , al lo win g sig n if i c a n t p o w e r s a vi n g s w h en t h e con v ersio n r a t e is r e d u ced (s e e f i gur e 32). th e ad7666 a u t o m a tical l y r e d u ces i t s p o w e r co n s um p t io n a t the en d o f eac h co n v er sio n p h as e . t h is m a k e s th e pa r t id eal f o r v e r y l o w po w e r ba t t e r y a p p l i c a t i o n s . the dig i t a l i n t e r f ace an d t h e r e fer e n c e r e main ac t i v e e v e n d u r i n g t h e acq u isi t io n pha s e . t o r e d u ce o p er a t i n g dig i t a l sup p ly c u r r en ts ev en f u r t h e r , digi tal in p u ts n e e d t o b e dr i v en c l ose t o th e p o w e r s u p p l y ra ils (i .e ., d v d d o r d g nd), a n d o v d d s h o u ld n o t exceed d v d d b y m o r e tha n 0.3 v . 03034-0-032 10 100 1k 10k 1m 10 100 1k 10k 100k 1m sampling rate (sps) pow e r d i ssipa tion ( w) pdref = pdbuf = high 100k f i g u re 32. p o wer d i s s i pat i on vs . sam p li ng ra t e
ad7666 rev. 0 | page 21 of 28 conversion control f i g u r e 33 s h o w s th e d e ta ile d tim i n g dia g ra m s o f th e co n v e r s i o n p r o c es s. th e ad7666 is co n t r o l l ed b y th e cnv s t sig n al , whic h ini t i a t e s con v ers i o n . once ini t ia te d , i t ca nn ot b e r e st a r t e d o r a b o r t e d , e v e n b y t h e p o w e r - down in p u t p d , u n t i l t h e con v ersi o n is co m p let e . cnv s t o p era t es i n dep e n d en t l y o f cs and rd . c o n v ersio n s c a n b e a u t o ma tica l l y ini t ia ted wi th the ad7666. i f cnv s t is h e l d lo w w h en b u s y is lo w , th e ad766 6 co n t r o ls t h e ac q u isi t ion phas e and a u t o ma t i c a l l y ini t i a tes a ne w co n v e r si o n . b y k eep i n g cnv s t l o w , t h e ad7666 k eeps th e co n v ersio n p r o c es s r u nnin g b y i t s e lf. i t sh o u ld b e n o t e d t h a t t h e a n alog in p u t m u s t be s e t t le d w h en b u s y g o es l o w . also , a t po w e r - u p , cnv s t s h o u ld be b r o u gh t lo w o n ce t o ini t ia t e t h e co n v ersio n p r o c es s. i n this m o de , th e ad7666 c a n r u n s l ig h t l y fas t er than the g u a r a n t e e d 500 ks ps. al th o u g h cnv s t is a dig i t a l sig n al , i t sh o u ld be desig n ed wi t h s p ec ial ca r e wi t h fast, c l ea n e d ges, a n d lev e ls wi th m i nim u m o v ersh o o t and un dersh o ot o r r i n g in g. the cnv s t trace s h o u l d b e s h ie lde d wi th gr o u n d an d a lo w val u e s e r i al r e sis t o r (i .e ., 50 ?) ter m ina t ion sh ou ld be adde d c l ose t o th e o u t p u t o f th e co m p o n en t tha t d r i v es th i s li n e . f o r a p plica t ion s wher e s n r is c r i t ica l , t h e cnv s t sig n al s h o u l d ha v e v e r y lo w ji t t er . t h is ma y b e ac hie v ed b y usin g a dedica t e d oscil l a t o r f o r cnv s t ge ne r a t i on , or to c l o c k cnv s t wi th a high f r eq uen c y , lo w ji t t e r c l o c k, as sh o w n in f i gur e 26. bu s y mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 a c q uire conver t a cq uire convert 03033-0-026 cnvst f i gure 33. bas i c co n v ersi on ti ming t 9 t 8 reset data busy 03033- 0- 027 cnvst f i g u re 34. r e se t ti ming t 1 t 3 t 4 t 11 bu s y da t a bu s cs = rd = 0 t 10 previous conversion d a t a new d a t a 03033- 0- 028 cnvst f i g u re 35. m a s t e r p a r a l l e l d a t a tim i ng f o r r e adi n g (cont i nuous r e ad)
ad7666 rev. 0 | page 22 of 28 digi tal in t e rface the ad7666 has a v e rs a t ile dig i tal in t e r f ace; i t c a n be in t e r f ace d wi t h t h e h o s t sy s t em b y usin g ei th er a ser i al o r a p a ral l e l i n t e rf a c e . t h e se ri a l i n t e rf a c e i s m u l t i p l e x e d o n th e pa r a ll e l d a ta b u s. the ad766 6 dig i tal in t e r f ace als o acco mm o d a t es bo th 3 v a n d 5 v logic b y sim p l y co nn ec t i n g the o v d d s u p p l y p i n o f t h e ad7666 t o t h e h o s t sys t em in ter f ace dig i tal s u p p l y . f i nal l y , b y usin g t h e o b / 2c in p u t p i n , bo th tw os co m p lem e n t o r s t ra i g h t b i na r y co di n g c a n b e us e d . the tw o sig n als, cs an d rd , c o n t r o l t h e i n t e r f a c e . cs an d rd ha v e a si mi l a r ef fe c t b e ca us e t h e y a r e o r d t o g e t h er i n t e r n al ly . w h en a t le ast on e o f t h es e sig n als is hi gh, t h e in t e r f ace o u t p u t s a r e in hi gh im pe d a n c e . u s uall y cs al lo ws th e s e lec t io n o f eac h ad7666 in m u l t icir c u i t a p p l ic a t ion s and is he ld lo w in a sin g le ad7666 desig n . rd is g e n e ral l y used t o en a b le the c o n v e r s i on re su lt on t h e d a t a bu s . parallel interf ace the ad7666 is co nf igur ed t o us e the p a ral l e l in t e r f ace when se r / pa r is h e l d lo w . th e da t a can be r e ad ei t h er af t e r eac h co n v ersio n , whi c h is d u r i n g t h e n e xt ac q u isi t ion phas e , o r d u r i n g t h e fol l o w i n g con v ersio n , as sh o w n i n f i gur e 36 a n d f i gur e 37, r e sp e c t i v e ly . w h en t h e da t a is r e ad d u r i n g t h e co n v er sio n , h o w e v e r , i t is r e co m m e n d e d tha t i t is r e ad o n l y d u r i n g the f i r s t half o f th e co n v er sio n p h ase . this a v o i ds an y po t e n t i a l f e e d thr o u g h bet w een v o l t a g e tra n s i en t s o n t h e di gi tal in t e r f ace a n d t h e m o st cr i t i c al analog co n v ersio n cir c ui t r y . t h e by t e sw ap p i n al lo ws a gl ue les s in t e r f ace t o a n 8-b i t b u s. a s sh o w n in f i gur e 38, th e ls b b y t e is o u t p u t o n d[7:0] a n d t h e ms b is o u t p u t o n d[15:8] w h en by t e sw ap is l o w . w h en by tes w ap is hi gh, t h e ls b a n d ms b b y t e s a r e swa p p e d and th e ls b is o u t p u t o n d[15:8] and the ms b is ou t p u t o n d[7:0]. b y co n n ectin g b y t e sw a p t o a n a d d r e s s lin e , th e 16-b i t d a ta ca n be r e ad in tw o b y t e s o n ei t h er d[15:8] o r d[7:0]. serial interface the ad7666 is co nf igur ed t o us e the s e r i al in t e r f ace when se r / pa r is h e l d hi gh. th e ad76 66 o u t p u t s 16 b i ts o f da ta , ms b f i rst, o n t h e s d o u t pin. this da t a is sy nchr o n iz e d wi t h t h e 16 clo c k p u ls es p r o v ide d on t h e sc lk p i n. the o u t p u t da t a is va lid o n b o t h t h e r i sin g and f a l l in g e d ges o f t h e d a t a clo c k. current conversion bu s y da t a bus t 12 t 13 03033- 0- 029 rd cs f i gure 36. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) previous conversion t 1 t 3 t 12 t 13 t 4 bu s y da t a bu s 03033- 0- 030 cnvst, rd cs = 0 f i gure 37. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead d u ring con v e r t) cs rd byteswap pins d[15:8] pins d[7:0] hi-z hi-z high byte lo w byte lo w byte high byte hi-z hi-z t 12 t 12 t 13 03033-0-031 f i g u re 38. 8-b i t p a r a l l e l int e r f a c e
ad7666 rev. 0 | page 23 of 28 master serial interface u s ual l y , be ca us e th e ad7666 is us ed wi t h a fas t thr o ug h p u t , t h e m a st er read d u r i n g c o n v er sio n m o de is t h e m o s t r e co mm en - de d s e r i a l m o de. i n t h is m o de, t h e s e r i a l clo c k and d a t a to g g l e a t a p p r o p ria t e i n s t a n t s , m i n i mi zi n g po t e n t i a l f eed t h r o u g h bet w een dig i t a l ac t i vity and cr i t ica l con v ersio n de cisio n s . inter n al cloc k the ad7666 is co nf igur ed t o gen e r a t e and p r o v ide t h e s e r i al da ta c l ock s c lk wh en th e ex t / in t p i n is h e l d lo w . th e ad7666 als o g e n e ra t e s a s y n c sig n al t o indic a te t o th e h o s t when t h e s e r i al da t a is v a lid . the s e r i al clo c k s c lk and t h e s y n c sign al can b e in v e r t e d if desir e d . dep e n d in g o n the rd c/s d in in p u t, th e da t a can be r e ad a f t e r eac h co n v er sio n o r d u r i n g t h e fol l o w in g con v ersio n . f i gur e 39 a n d f i gur e 40 s h o w d e ta ile d ti mi n g d i a g ra m s o f th ese t w o m o d e s. i n read af t e r c o n v ersio n m o de, i t sh o u ld be n o t e d t h a t unli k e in o t h e r mo des, t h e b u s y sig n al r e t u r n s l o w af t e r t h e 16 da t a b i ts a r e p u ls e d ou t an d n o t a t t h e end o f t h e con v ersio n phas e , w h ich r e su lts i n a lo n g er b u s y wi d t h. t 3 bu s y sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 12 3 1 4 1 5 1 6 d15 d14 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 03033-0-032 cnvst cs, rd ext/int = 0 f i gure 39. mas t e r s e ri al d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 1 4 1 5 1 6 t 18 bu s y sync sclk sdout 03033-0-033 cnvst cs, rd f i g u re 40. m a s t e r s e ri al d a t a tim i ng f o r r e adi n g (r ead pr ev i o us convers i on duri ng co nve r t )
ad7666 rev. 0 | page 24 of 28 slave serial interface extern al c l oc k the ad7666 is co nf igur ed t o acce p t an ext e r n al l y s u p p lied se ri al d a t a c l oc k o n th e s c lk p i n wh en t h e ex t / in t pi n i s h e l d hi gh. i n t h is m o de , s e v e r a l m e t h o d s can be use d t o r e ad t h e da t a . th e ext e r n al s e r i al clo c k is ga t e d b y cs . w h e n cs an d rd a r e bo th l o w , th e da ta ca n be r e a d a f t e r ea ch co n v e r s i o n o r d u r i n g t h e fol l o w i n g con v ersio n . th e ext e r n al clo c k can b e e i t h e r a c o n t i n u o u s or a d i s c on t i n u ou s c l o c k . a d i s c on t i n u ou s clo c k can b e ei t h er n o r m al ly hi gh o r n o r m al ly l o w w h en inac t i v e . f i gur e 41 a n d f i gur e 4 2 s h o w t h e de t a i l e d t i min g dia g ra m s o f th es e m e tho d s. u s ual l y , bec a us e t h e ad7666 has a lo n g er acq u isi t i o n phas e t h a n c o n v ersio n phas e, t h e da t a a r e r e ad imm e dia t ely a f t e r co n v ersi o n . w h ile t h e ad7 666 is p e r f o r m i n g a b i t decision, i t is im p o r t an t th a t v o l t a g e tra n s i e n t s be a v o i ded o n d i gi tal in p u t / o u t p u t p i n s or d e g r a d a t i o n of t h e c o n v e r s i on re su lt c o u l d o c c u r . t h i s i s p a r t ic u l a r ly im p o r t a n t d u r i n g t h e s e con d half o f t h e con v ersio n p h as e bec a us e t h e ad7666 p r o v ides er r o r co r r ec tio n cir c ui tr y tha t c a n co r r ec t f o r a n im p r o p er b i t decisio n made d u r i n g t h e f i r s t h a l f of t h e c o n v e r s i on ph a s e. f o r t h i s re a s on , it i s r e co mme n d e d t h a t when an exter n a l clo c k is b e in g p r o v ide d , i t is a dis c on t i n u o u s clo c k t h a t is tog g l in g o n ly w h en b u s y is l o w , o r , m o r e im po r t a n tl y , tha t i t d o e s n o t tra n s i ti o n d u ri n g t h e l a t t er half o f b u s y hi g h . sclk sdout d15 d14 d1 d0 d13 x15 x 1 4 x13 x1 x0 y15 y14 bu s y sdin invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x 1 4 x 1 2 3 1 4 1 51 61 7 1 8 t 34 03033-0-034 ext/int = 1 rd rd = 0 f i gure 41. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead a f te r co n v e r t) s dout sclk d1 d0 x d15 d14 d13 12 3 1 4 1 5 1 6 t 3 t 35 t 36 t 37 t 31 t 32 t 16 bu s y ext/int = 1 invsclk = 0 03033-0-035 cnvst cs rd = 0 f i gure 42. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead p r e v ious con v ers i on d u ring con v e r t)
ad7666 rev. 0 | page 25 of 28 extern al discontinuous clo c k data read after conv ersion th o u g h t h e maxim u m t h r o ug h p u t cann o t be ac hie v e d usin g this m o de , i t is t h e m o s t r e co mm en ded o f t h e s e r i al s l a v e m o de s. f i gur e 41 sh o w s t h e de t a i l e d t i min g di ag r a m s o f t h is me t h o d . af te r a c o n v e r s i on i s c o m p l e te, i n di c a te d b y b u s y re tu r n i n g l o w , t h e c o n v e r s i o n s re su lt c a n b e re a d w h i l e b o t h cs an d rd a r e l o w . da t a is s h if t e d o u t ms b f i r s t wi t h 16 c l o c k p u ls es a n d is va l i d o n t h e r i sin g a n d f a l l in g e d ge s o f t h e clo c k. a m o n g th e a d v a n t a g e s o f t h i s m e th od i s th e f a ct t h a t co n v ersio n p e r f o r ma n c e is n o t deg r ade d b e c a us e t h er e a r e n o v o l t a g e t r a n sie n ts o n t h e dig i t a l in t e r f ace d u r i n g t h e con v ersio n p r o c ess. an o t h e r ad va n t a g e is t h e ab i l i t y t o r e ad t h e da t a a t an y s p ee d u p t o 40 mh z, w h ic h acc o m m o da t e s bo t h the s l o w digi t a l h o st i n t e r f ace and t h e fast est s e r i al r e ading. f i nal l y , in this m o de o n l y , the ad7666 p r o v ides a da isy-c h a i n fe a t ur e usin g t h e rd c/s d in p i n fo r cas c ading m u l t i p le con- v e r t ers t o g e t h er . this fe a t ur e is us ef u l fo r r e d u cin g co m p on e n t co un t and wir i ng co nnec t io n s when desir e d , as, f o r in s t a n ce , in i s o l at e d mu l t i c o n v e r t e r ap p l i c at i o n s . an exa m ple o f t h e conca t ena t ion o f tw o de vi ces is sh o w n i n f i gur e 43. s i m u l t a n e o us s a m p lin g is p o s s ib le b y usin g a co mm o n cnv s t sign al . i t s h o u ld be n o t e d tha t t h e rd c/s d i n in p u t is l a t c h e d o n t h e o p p o si te e d g e o f sclk of t h e on e us e d to shif t o u t t h e da t a o n sd o u t . th er efo r e , t h e m s b o f t h e u ps tr ea m co n v e r t e r j u s t f o llo w s th e l s b o f th e d o w n s tr ea m co n v er t e r o n t h e n e xt sc lk c y cle . sclk sdout rdc/sdin bu s y bu sy data out ad7666 #1 (do wnstream) busy out sclk ad7666 #2 (upstream) rdc/sdin sdout sclk in cnvst in 03034-0-036 cnvst cs cnvst cs cs in f i g u re 43. t w o a d 7 6 6 6 s in a d a is y- ch ain conf ig ur at i o n extern al cloc k dat a r e ad d u ring con v e r sion f i g u r e 42 s h o w s th e d e ta ile d tim i n g dia g ra m s o f th i s m e t h o d . dur i n g a co n v er si o n , wh ile bo t h cs an d rd a r e l o w , t h e r e su l t o f t h e p r e v io us co n v ersio n can b e r e ad . th e da t a is shif t e d ou t ms b f i rst wi t h 16 clo c k p u ls es, a n d is vali d o n b o t h t h e r i sin g a n d fal l in g edg e s o f th e c l o c k. th e 16 b i ts m u s t be r e ad b e f o r e t h e c u r r en t con v ersio n is co m p let e ; o t h e r w i s e , rd err o r is pu l s e d hig h and c a n b e u s e d to i n te r r u p t t h e ho st i n te r f ac e to p r e v en t i n com p let e da t a r e adi n g. th er e is n o da isy-cha i n fe a t u r e in t h is m o de and t h e rd c/s d i n in p u t sh o u ld a l wa ys b e t i e d ei t h er hi gh o r l o w . t o r e du c e p e r f o r m a n c e d e g r a d at i o n du e t o d i g i t a l a c t i v i t y , a f a s t d i s c on t i n u ou s c l o c k of a t l e a s t 1 8 m h z i s re c o m m e n d e d to en sur e t h a t al l t h e b i ts a r e r e ad d u r i n g t h e f i rst half o f t h e co n v er sio n p h as e . i t is also p o s s i b le t o b e gin t o r e ad da ta a f t e r co n v ersio n an d co n t in ue t o r e ad the las t b i ts a f t e r a n e w co n v ersio n has b e e n ini t ia t e d . this al lo ws t h e us e o f a slo w er c l o c k s p e e d li k e 14 mh z.
ad7666 rev. 0 | page 26 of 28 microprocessor interfacing the ad7666 is ideal l y s u i t e d fo r tradi t io nal dc m e as ur em en t ap p l i c at i o n s s u p p o r t i n g a m i c r o p r o c e s s o r , a n d f o r a c s i g n a l p r oce s si n g a p p l ica t i o n s in t e rfa c in g t o a di gi tal sign al p r oce s so r . the ad7666 is desig n e d t o in t e r f ace ei ther wi t h a p a ral l e l 8-b i t o r 16-b i t wide in t e r f ace , o r wi t h a g e n e ral-p u r p ose ser i al p o r t o r i / o p o r t s on a m i c r o c on t r o l l e r . a v a r i e t y of e x te r n a l bu f f e r s c a n be us e d wi t h the ad7666 t o p r ev en t dig i tal n o is e f r o m co u p ling in t o t h e ad c. th e fol l o w in g s e c t io n dis c uss e s t h e us e o f an ad7666 wi t h an ads p -219x s p i eq ui p p e d ds p . spi interface ( a dsp-219x) f i gur e 44 s h o w s a n in t e r f ace diag ra m betw e e n t h e ad7666 and th e s p i eq u i p p e d ads p -219x. t o acco mm o d a t e th e s l o w er s p ee d o f th e ds p , th e ad7666 ac ts as a sla v e de vice and da ta m u s t be r e ad a f ter co n v er sio n . this m o de also al lo ws th e da isy- cha i n fe a t ur e . th e con v er t co mma n d c a n b e ini t ia t e d in re sp ons e to an i n te r n a l t i me r i n te r r u p t . the re a d i n g pro c e s s c a n be in i t ia t e d in r e s p o n s e t o th e en d - o f - c o n v e r s i o n si gn al (b us y g o in g lo w ) usin g a n in t e r r u p t lin e o f t h e ds p . the s e r i al in ter - face (s p i ) o n t h e ads p -219x is co nf igur ed fo r m a s t er m o de (ms t r) = 1, c l o c k p o la r i ty b i t (cpo l) = 0, c l o c k p h as e b i t (cp h a) = 1, a n d s p i i n t e r r u p t ena b le ( t im o d ) = 00b y wr i t i n g t o t h e sp i co n t r o l r e g i ster (s p i cl tx). t o m e et al l t i mi ng r e q u ir em e n ts, t h e sp i clo c k sho u ld b e li mi t e d t o 17 mb ps, whic h al lo ws i t t o r e ad a n ad c r e s u l t in les s tha n 1 s. w h en a hig h er s a m p li ng ra t e is desir e d , us e o f o n e o f t h e p a ral l e l in t e r f ace m o des is r e co mm e n de d . ad7666* adsp-219x* ser/par pfx misox sckx pfx or tfsx bu s y sdout sclk cnvst ext/int cs rd invsclk dv d d * additional pins omitted for clarity spixsel (pfx) 03034-0-037 f i g u re 44. inte r f a c i n g t h e a d 7 6 6 6 to a n spi inte r f ace
ad7666 rev. 0 | page 27 of 28 appli c ation hints bipolar and wider input ranges i n so m e a p p l ica t io n s , i t is d e sirab l e t o use a b i po la r o r w i d e r a n alog in p u t ran g e s u c h as 10 v , 5 v , o r 0 v t o 5 v . al th o u gh th e ad7666 has o n l y o n e uni p ola r ra n g e , sim p l e m o dif i c a tio n s o f in p u t d r i v er cir c ui tr y all o w b i po la r an d w i der in p u t ran g es t o b e u s e d w i t h out an y p e r f or m a n c e d e g r a d at i o n . f i g u r e 4 5 show s a co nn ecti o n dia g ra m tha t allo w s th i s . c o m p o n en t v a l u e s r e q u ir e d and r e su l t in g f u l l -s ca l e ra n g es a r e sh o w n in t a b l e 8. w h en desir e d , acc u ra t e ga in an d o f fset ca n be c a li b r a t e d b y acq u ir in g a g r oun d an d v o l t a g e r e fer e n c e usin g a n a n a l og m u l t i p lexer (u2), as s h o w n in f i gur e 45. 03034-0-038 u1 analog input r2 r3 r4 100nf r1 u2 c ref in ingnd ref refgnd ad7666 c f 15 ? 2.7nf f i g u re 45. u s ing t h e a d 7 6 6 6 in 16- bit bipo l a r and/ or wid e r input rang es table 8. co mpone n t values a n d input rang es input range r1 (?) r2 (k?) r3 (k?) r4 (k?) 10 v 500 4 2.5 2 5 v 500 2 2.5 1.67 0 v to C5 v 500 1 none 0 layout the ad7666 has v e r y g o o d imm u ni ty t o n o is e o n the p o w e r s u p p lies. h o w e ver , ca r e s h o u ld stil l be t a k e n wi t h r e ga r d t o gr o u n d i n g la y o u t . the p r in te d cir c ui t b o a r d t h a t ho us es t h e ad76 66 sh o u ld b e desig n e d s o t h e a n a l o g a n d dig i t a l s e c t io n s a r e s e p a r a te d an d c o n f i n e d to c e r t ai n are a s of t h e b o ard. th i s f a c i l i t a te s t h e u s e of gr o u n d p l an es t h a t c a n be s e p a ra t e d easil y . dig i tal an d a n alog g r o u n d pl an es sh o u ld b e j o i n e d in o n ly on e place , p r efera b ly un der n ea t h t h e ad7666, o r as c l os e as p o s s i b le t o th e ad7666. i f th e ad7666 is in a sys t em w h er e m u l t i p le devices r e q u ir e a n alog - t o- d i g i tal gr o u n d co nn e c ti o n s , th e co nn ecti o n s h o u ld st i l l b e m a d e a t one p o i n t on l y , a st ar g r ou n d p o i n t t h a t s h ou l d b e est a b l ish e d as clos e as p o ssi b le t o t h e ad766 6. r u nnin g dig i t a l lin e s u n der t h e de vice sh o u l d b e a v o i d e d si n c e t h es e wi l l cou p le n o is e o n t o t h e die . th e analog g r o u n d pl an e s h o u ld b e al lo w e d t o r u n under th e ad7666 t o a v o i d n o is e co u p lin g . f a st s w i t c h in g sig n als lik e cnv s t or c l o c k s s h ou l d b e sh i e l d e d w i t h d i g i t a l g r ou n d to a v oi d r a d i a t i n g noi s e to ot he r s e c t i o ns of t h e b o ard, a n d s h ou l d n e ve r r u n ne ar an a l o g s i g n a l p a t h s. cr os s o v e r o f dig i t a l and a n alog sig n als s h o u ld be a v o i de d . t r aces o n dif f er en t b u t clos e l a yers o f t h e b o a r d sh o u ld r u n a t r i gh t a n gles t o e a c h o t h e r . t h is wil l r e d u ce t h e ef f e c t o f cr os s t al k th r o u g h th e boa r d . the p o w e r s u p p l y lin e s t o t h e ad7666 sh o u ld us e as la rg e a t r ace as p o ssib le t o p r o v ide lo w im p e dance p a t h s a n d r e d u c e t h e ef f e c t o f gli t c h es o n the p o w e r su p p l y lin e s. go o d deco u p lin g is als o im p o r t a n t to lo w e r t h e su pply s im p e dance p r es en t e d t o t h e ad7666 an d t o r e d u ce t h e ma g n i t ude o f th e s u p p l y s p ik es. deco u p lin g cera m i c c a p a ci t o rs, typ i cal l y 100 nf , s h o u ld be p l a c e d on e a c h p o we r s u pp l y pi n a v dd , d v dd , and o v d d clos e to , a n d i d e a l l y r i g h t u p a g ain s t t h es e p i n s and t h eir co r r esp o ndin g g r o u n d pi n s . a d di t i o n al ly , lo w es r 10 f c a p a c i tors s h ou l d b e l o c a te d ne ar t h e a d c to f u r t he r re d u c e lo w f r eq uen c y ri p p le . the d v d d su pply o f t h e ad76 66 ca n b e a s e p a ra t e su p p ly , o r ca n co m e f r o m th e a n alog s u p p l y a v d d o r th e d i gi tal i n t e rfa c e s u p p l y o v d d . w h en t h e syst em dig i t a l su p p l y is n o isy o r w h en fas t swi t c h in g digi tal sign als a r e p r esen t, if n o sep a ra t e s u p p l y is a v a i la b l e , t h e us er s h o u ld co nn e c t d v dd t o a v d d thr o ugh a n r c f i l t er (s e e f i gur e 26) a n d t h e syst em su p p ly t o o v d d an d th e r e m a i n i n g di gi tal ci r c u i tr y . w h e n d v d d i s po w e r e d f r o m t h e system su p p ly , i t is us ef u l t o in s e r t a b e ad t o f u r t h e r r e d u ce hig h f r e q ue n c y sp i k es. the ad7666 has f i v e dif f er en t g r o u n d p i n s : ingnd , refgnd , a g nd , d g nd , and o g nd . i n gnd is us e d to s e n s e t h e ana l o g in p u t sig n al. re fgnd s e n s es t h e r e fer e nce v o lt a g e and , b e c a us e i t c a rri e s p u l s ed cu rr e n t s , s h o u l d be a l o w i m ped a n c e r e t u rn t o t h e r e fer e n c e . a g nd is t h e g r oun d t o which most in t e r n a l ad c a n alog si gn als a r e r e f e r e n c ed ; i t m u s t be co nn ec t e d wi th t h e leas t r e sis t an ce to th e a n alog gr o u n d plan e . d g n d m u s t be tie d to t h e an a l o g or d i g i t a l g r ou nd pl a n e d e p e nd i n g on t h e c o n f i g - ur a t io n. o g nd is co nne c t e d to t h e d i g i t a l sy ste m g r o u nd . evaluating the ad7666s performance a r e co mm en de d l a yo u t fo r th e ad7666 is o u tlin e d in the e v al -ad7666 eval ua tion bo a r d fo r th e ad766 6. th e e v a l ua t i on b o a r d p a ck a g e i n cl u d es a f u l l y ass e m b le d and teste d e v a l u a t i on b o ard, d o c u me n t a t i o n , an d s o f t w a re for c o n t rol l i n g t h e b o a r d f r o m a pc vi a t h e ev a l - c on trol br d 2 .
ad7666 rev. 0 | page 28 of 28 outline dimensions top view (pins down ) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc s q seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 10 6 2 0.15 0.05 compliant to jedec standards ms-026bbc figure 46. 48-lead quad flatpack (lqfp) [st-48] dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0.25 min 0.20 ref compliant to jedec standards mo-220-vkkd-2 figure 47. 48-lead frame chip scale package (lfcsp) [cp-48] dimensions shown in millimeters ordering guide model temperature range package description package option ad7666ast C40c to +85c quad flatpack (lqfp) st-48 ad7666astrl C40c to +85c quad flatpack (lqfp) st-48 ad7666acp C40c to +85c lead frame chip scale (lfcsp) cp-48 AD7666ACPRL C40c to +85c lead frame chip scale (lfcsp) cp-48 eval-ad7666cb 1 evaluation board eval-control brd2 2 controller board 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03034C0C1/04(0)

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